Research On Reliability Of Reconfigurable Computing Unit

Reconfigurable computing uses a special structural design with the flexibility of a general-purpose processor and the efficiency of an ASIC.It is often used in high-performance computing such as multimedia data processing,data transformation processing,and pattern recognition.However,as semiconductor manufacturing processes continue to decrease,the stability of electronic devices has dropped dramatically.A variety of high-energy particles in the aerospace industry make electronic devices susceptible to Single Event Upset.In the current heterogeneous multi-core computing system,the reconfigurable computing unit is an important computing unit in the system.There is no reasonable fault-tolerant mechanism for the single-event flipping problem,and its reliability cannot be guaranteed.In response to this problem,this dissertation studies the reliability of the existing reconfigurable computing unit of the system.The main work is as follows:Firstly,combined with the structural features of the current reconfigurable computing unit and the functional role in the system,different fault-tolerant schemes are proposed for different modules.Because the control layer has few resources but the logic is complex,the three-module redundancy scheme is adopted.Because the computing layer has computational resource redundancy,the specific fault-tolerant scheme is adopted according to the operation type;the information redundancy in the storage layer is used,and the logical resource adopts three-mode redundancy.Then,the fault-tolerant scheme of the reconfigurable arithmetic unit is specifically designed and implemented.The control layer adopts the three-mode voting design and simultaneously changes the multiple modules in the control layer;the design of the comparator in the operation layer is implemented at the same time,and the internal modification of the execution component is realized to realize the optimized rewinding of the correlation data stream operation;The Hamming code reinforced the storage device and performed a three-mode voting design for the remaining logic devices.Finally,the implementation of the RTL model and the prototype verification were completed according to the reliability design.The structural and functional tests are performed on the reconfigurable arithmetic unit with fault tolerance,which achieves the same effect as the original reconfigurable arithmetic unit;it has 58.1% additional resource overhead compared to the original reconfigurable arithmetic unit.With a small amount of extra time overhead,a reliability rate of more than 99% is achieved,and the reliability study of the entire reconfigurable arithmetic unit is completed.