Reasarch And Design Of UVM-Based AXI Verification Technology

With the promoting scale and complexity of digital IC designs,the requirements for verification also become more and more strict.The quality of verification is the most critical factor effecting the quality of chip in present day.The industry developed UVM on the basis of SystemVerilog in order to improve the efficiency of verification and reduce the time and labor cost of chip development.This new verification methodology featuring object-oriented programming concept,is flexible with excllent scalability and reusability,and is becoming the dominated verification technology in the field of digital IC.AXI bus featuring high bandwidth and low latency,and the main transmission mode is burst transmission.It supports outstanding transmission,out-of-order transmission and interleaving operation.Multiple masters and slaves can be connected via AXI bus.It can improve the amount of data transmission effectively,in hence,is widely used in the design of SoC because it can boost the performance of the SoC significantly.A verification platform targeting to verify AXI protocol is developed based on UVM technology.This platform features good configurability,reusability,clean module hierarchy and code,can output a variety of complex stimulus.Three testcases,random test,base test and error test,are designed to to verify a Block RAM IP featuring AXI4 Interface.A simulation verification platform with multi-master and multi-slave interconnections is also built to verify interconnected multiple AXI devices by using these three testcases.The final ratio of function coverages in simulation reaches 100%.The simulation results show the correct functionality of the designed verification platform.This platform can meet the requirements for verifying AXI bus,and improve efficiency of verifying SoC with built-in AXI bus.