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Research And Implementation Of The Turbo Product Code

Posted on:2015-06-04Degree:MasterType:Thesis
Country:ChinaCandidate:J C MaFull Text:PDF
GTID:2298330422493474Subject:Electronics and Communications Engineering
Abstract/Summary:PDF Full Text Request
In a communication system, how to ensure the validity and reliability of theinformation transmission are two important problems. The Turbo product code gets people’sattention because of its good error correction performance. In decoding, it use soft inputsoft output (SISO) iterative decoding algorithm and it use the same decoding method asTurbo codes. Although the BER performance of Turbo codes is similar with theperformance of the Turbo product code, the decoding complexity of Turbo product code islower than Turbo codes. Therefore, the Turbo product code has become a hot research fieldof the coding area in recent years, and it will be widely applied in high speedcommunication system which requires high transmission rate.In this paper, the author introduces the structure and the encoding method of Turboproduct codes. Sub code can consist of the same or different codeword and we can choosethe BCH code, the extended Hamming code or parity check code to be the sub-code. Afterthat, the author introduces the decoding principle of Turbo product codes. The decodingalgorithm has Chase algorithm, Cyclic-2PML algorithm and dB algorithm. In this paper theauthor uses Chase decoding algorithm.In this paper, the author uses the BCH code as a sub-code and there are combination offour kinds of modulation modes and four kinds of bit rate. The important point is that wecan use different combinations of encoding and decoding methods when the demand ofSNR is different. Through Matlab simulation, we chose eight kinds of coding modulation tomeet the need of our project.Finally the author describes the realization method of encoder and decoder of Turboproduct code by FPGA. We first introduce the overall design scheme of encoder anddecoder, and then we explain the realization process and the main function of each module.The hardware description language and IDE adopted are Verilog HDL and ISE12.0. Theencoder and decoder are respectively compiled and simulated in virtex4SX55and virtex5FX130T by ISE12.0.
Keywords/Search Tags:TPC, shorten codes, Chase algorithm, Soft demapping
PDF Full Text Request
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