Design And Implementation Of FPGA Subsystem In Improved Data Link Terminal

As an information transmission system that links various combat arms,the tactical data link plays an indispensable role in today's modern warfare.Thr-ough this system,the command center can obtain the information of each combat unit and weapon platform in real time.Thus,an accurate judgment on the battlefield situation can be made and the battlefield initiative can be mastered finally.Through the research on tactical data links,an improved data link based on the existing hardware platform is designed and implemented in this work.Compared with the original link,the improved data link improves the link transmission rate,information capacity,and transmission delay.Specifically,FPGA is the main logic chip in the data link terminal.While completing the signal processing function in th e data link terminal,FPGA is also responsible for the time slot management of the whole board and the control of the peripheral chip.The work of this thesis is to focus on the design and implementation of the FPGA subsystem in the data link terminal.First of all,this thesis introduces the background and significance of the research.After expounding the necessity of researching the tactical data link system,the main work content and structure of the thesis are introduced mainly.Secondly,this thesis gives a general description of the tactical data link terminal.The key technologies used in the data chain design and implementation process are introduced,and the improved data link to be completed performance indicators are given.Thirdly,this thesis designs and implements the transmitting module and receiving module in the data link terminal according to the order of transmission of information stream in the data link.At the same time,this thesis analyzes the design and implementation of multi-rate signal processing,cross-clock domain signal transmission and synchronization logic involved in the module.Finally,the correctness of the system design in our work is verified by the simulation of the function module,the verification of the FPGA subsystem and the overall test of the data link terminal.