Research On Digital Down Conversion Using FPGA

Today, in the field of wireless communication, because of limit by sample speedof A/D conversion& processing speed of digital signal processor, RF signal istransferred to intermediate frequency signal, including mixer, decimation, filter, andthen processed. After digital down conversion, high-speed signal is switched tolow-speed signal, and processed by DSP or CPU in baseband.In this paper, digital down conversion is researched. During sample in IF,bandpass sample is introduced to complete sample using low-speed, limit is brokendown in traditional low-pass sample. Arbitrary sinusoid is generated by NCO basedon DDS technology, after mixer, IF signal can be transferred to baseband signal.Multi-rate processing theory is the base of accomplishing high-speed to low-speed;the key technology is how to design anti-mixer filter. In the paper, a kind of filterwithout multiplier this is CIC filter is introduce and designed, especially adapted inhigh-speed situation. Meanwhile, FIR based on distribution arithmetic is designed,completed architecture of multiplier adder efficiently.Dspbuilder, a kind of design tools is used in the paper. From the top of system,NCO, CIC filter, FIR filter is accomplished in a fiat. Simulation, synthesis, downloadcan be operated in the flat. In the end, design can be checked on RTL system.