Sampling And Strengthen The Function Of High-voltage Dmos Design Radiation-hardened

Power VDMOS is not only widely used in household electrical appliances、 industrial control and other fields, but also used in the power electronic systems of the nuclear and the space environment. There are ionizing irradiation and single-particle irradiation in the nuclear and the space environment. The radiation makes VDMOS devices’characteristics worse, even failure. So the research of enhancing the ability of anti-irradiation of VDMOS is very meaningful. Moreover, VDMOS is oftern used in over current environment. Therefore, there is an urgent need of VDMOS to have sampling function to control and protect the VDMOS and its applications. View of this, in this paper, a novel500V VDMOS with functions of anti-total dose radiation and sampling is studied. The work of this paper is as follows:Firstly, the500V VDMOS is designed, including drawing up its process and designing its cell and termination. Associated with the requirement of anti-total dose irradiations in VDMOS, late gate process and square cell structure are adopted. Late gate processing can reduce gate oxide fixed charges and interface states introduced by the thermal process to improve the quality of the gate oxide and the ability of anti-total dose irradiation of the device. The simulation results show that:after irradiating the device with total dose of200Krad(Si), the breakdown voltage of the device shortened by about60V, and the threshold voltage shifts about0.818V. Therefore, the device has the ability of anti200Krad(Si) total dose radiation.Secondly, the sampling structure has been studied. The global current sampling method will lead the increasing circuit-resistance which will increase the consumption of the circuit rapidly. View of this, this design uses local current sampling and designs four kinds of layout structure with sapling rate1:4. The four kinds use cell, banding pbody diffusion well formed by pbody mask, termination with and without stop ring respectively to insulate cell and main cell region. Because the manufacturing of the chip has not yet completed, the wafer results have not been obtained.