Comprehensive Application Of SVA-Based Formal Verification And UVM

Verification plays a very important role in the development process of So C,which already account for 55% in average in the project time.Even so,most chips require 2 or more spins before mass production,and the functional defects are the number one reason to chip respins.With the pressures of more complex circuit functions and faster product launch,functional verification has become a bottleneck in the chip design and development cycle.Taking good use of existing verification tools and making a deep research on their verification characteristics is critical to ensure the correct function of the chip and improve the verification efficiency.According to this problem,this paper begins with module level verification and selects the two most popular verification methods used for module level verification to study.This paper takes the Multi Core Debug module as a verification case,uses the SVA-based formal verification and UVM to verify this module,and records the workload of various stages of the two verification methods when verifying it.This has led to the discovery of circuit features that apply to these two verification methods.Then in accordance with different circuit characteristics,a suitable verification method for comprehensive verification is selected.Analyze and compare these three verification methods in the establishment of the platform,the development and debugging of assertions,the development and debugging of test cases,and the workload of coverage rate analysis.The advantages and disadvantages of these three verification methods are summarized,and the suggestion of comprehensive using two verification methods is given combined with actual projects.In the research process of this paper,for formal verification,the proof coverage is 93.96%,the functional coverage is 100%;for UVM verification,the code coverage is 92.25%,the functional coverage is 100%,and they all meet the verification requirements after analysis.It is found that the circuit with more complex sequence signals is more suitable for verification using UVM,which saves 8 hours.The comparably more combination circuits are more suitable for the use of formal verification method to traverse,which saves 16 hours.The comprehensive verification method divides the Multi Core Debug module according to the circuit characteristics,and then verifies it.Comparing with the two separate verification methods,comprehensive verification saves 12.8% and 14.6% verification time,and the only disadvantage is that there is a risk of coverage rate for cross-platform statistics.In order to offset this deficiency,the comprehensive verification method is combined with the actual project process.According to different stages of development,an appropriate verification method is selected,and a verification processes starting with UVM and then transitioning to formal verification is proposed.The improved integrated verification method saves 8.5% and 10.4% verification time compared with the two separate verification methods.And it guarantees the quality of verification,because of the verified module finished verification by the formal verification standard.