A 16bit,200Msps ADC Data Acquisition System Design

With the rapid development of the semiconductor industry and semiconductor technology,analog-to-digital conversion chips,data storage chips,and control chips are increasingly improving in process and design progress,which provides a solid hardware foundation for higher performance data acquisition systems..The data acquisition system is a multi-module signal processing system that converts an external analog signal into a digital signal and performs data processing and transmission.With the rapid development of the electronic information industry,the demand for high-performance data acquisition systems is increasing.High-speed,high-precision data acquisition systems have become the solution for many scenarios such as medical equipment,driverless,and high-precision navigation.In recent years,communication technology has been iteratively developed,and various communication interface technologies have emerged in an endless stream.Under the premise of satisfying the sampling speed and accuracy of the data acquisition system,fast and stable data transmission has become a new trend in the development of acquisition systems.The data acquisition system introduced in this paper is based on the design scheme of ADC+FPGA.The ADC chip is the AD9467 chip designed and developed by Analog Devices.The sampling rate of this chip is 200Msps,the sampling precision is 16bit,which is a sampling speed and sampling.High performance ADC chip with precision.The FPGA selects the Virtex-6 chip developed by Xilinx.The specific model is XC6VLX240T-2FF1156.This FPGA uses a 40nm copper CMOS process.It has sufficient logic resources and storage resources for development and design.The FPGA has a high 10 of 1.3Gbps.Transceiver rate,can meet the receiving requirements of high-speed data transmission of AD9467.The design uses Gigabit Ethernet as the data transmission interface.Gigabit Ethernet transmission has the advantages of low latency,large data transmission,etc.,and the Ethernet interface has a wide range of applications in terminal hardware products.Laptops,mainframes,etc.are equipped with an Ethernet interface,which facilitates interconnection and data transmission of a variety of terminal products(laptops,desktops)and acquisition systems during experimental debugging,increasing the flexibility of the application of the acquisition system.Due to the high sampling rate of the ADC and the pressure on the data transmission of the system,the DDR3 memory stick is selected as the high-speed storage device of the system,which can reduce the limited storage resources inside the FPGA and cooperate with the IP address of the DDR3 controller provided by Xilinx.Core,complete the read and write control of DDR3,in order to simplify the development of the memory core model with integrated timing parameters in the IP core,namely MT4JSF12864HZ produced by Magnesium,the storage capacity is 2GB,and the working voltage is 1.5V.Based on the Gigabit Ethernet data transmission interface,the host computer software is designed to facilitate the user to control the operation of the data acquisition system and the data transmission and reception on the computer.The transmission channel of Ethernet is implemented on the basis of MAC layer.It does not support TCP/IP protocol.Therefore,Winpcap technology is used to capture data frames directly at the MAC layer,and cooperate with the lower computer to complete data transmission tasks.The paper also introduces the test scheme of the acquisition system,tests and analyzes the ADC static performance,dynamic performance,Ethernet transmission performance and DDR3 storage performance of the acquisition system;discusses various performance indicators for the data acquisition system.Significance,evaluation of the test results,and based on the test summarizes the system design advantages and areas for improvement.The work involved in this paper mainly includes the chip selection in the early stage,the drawing of the schematic diagram and board diagram of the acquisition system,the design of the data transmission logic,the design of the host computer software,and the testing of the acquisition system.Through reasonable hardware design,the effective bit of the data acquisition system is close to 12 bits,achieving high conversion accuracy at a high sampling rate of 200Msps.The overall work of the thesis is a closed-loop research and development process from design to simulation to testing,which can provide reference and reference for designers who follow the development of data acquisition systems.