Research And Implementation Of Turbo Encoder And Decoder In Power Line Communication System

With the development and progress of our society,people become more and more interested in high-speed,safe,efficient communication system and equipment.In daily life,power line carrier communication system is more and more widely used.And with the development of science and technology,it has the potential to replace cable in the future and save the laying of the network wire.At present,broadband power line carrier communication chips rely mainly on imports,because the domestic broadband power line technology is not mature yet.Therefore,the new requirements require people to develop a new technology to change the current situation as soon as possible.In the power line carrier communication,the channel coding and decoding has drew more and more attention.In this thesis turbo code is applied to power line carrier communication system,it improves the ability of anti-jamming communication system.This will reduce BER of the receiver's data and improve the performance of communication system.This thesis focuses on the design of turbo encoder and decoder in the physical layer of OFDM power line carrier communication.Compared MAP algorithm with SOVA algorithm,this thesis chooses SOVA algorithm of decoder with limiting operation and completes the algorithm of turbo encoder and decoder with MATLAB in power line communication system chip and reduces the bit error rate of the data.According to the algorithm,it implements the hardware of turbo encoder and decoder with the sliding window structure decoder by using DC and achieves 100 MHz at SMIC55nm process.Considering cost,speed,hardware complexity,delay information,this thesis adopts module sharing technology.It reduces the area and power consumption of chip,completes optimization of speed and area,improves the throughput of the system.After the synthesis is completed,through netlist simulation and formal verification,it ensures the accuracy of the design.At last,this thesis completes the realization of the hardware of the module by FPGA.Compared with the traditional MAP algorithm and improved algorithm,the improved algorithm of this thesis can not only save more RAM space,but also can improve the ability of anti-jamming of the channel.On the other hand,it reduces the area of the chip as well as the cost of design and manufacturing,etc.And it provides a powerful solution for low-power power line carrier communication chip.