Back-end Design Of High-performance Graphics Chip's Sub-module Based On 7nm Technology

As the technology of the integrated circuit has reached the deep nanometer level,there are more and more serious challenges for the back-end design to deal with.As foundry has adopted a new process technology,new design rules are needed to guide the overall back-end design,which requires changing the complete flow of the back-end design;and the chip scale is gradually increasing to several billions or more,and the chip interconnection is getting accumulatively complex,the metal layers'number is more than 12,and the manufacturability issues such as antenna effect and via failure also need to be considered in the back-end design in advance;at the same time,progressively increased crosstalk will also affect the timing enclosure;the increased chip size,and the increase in interconnect complexity has also made routing congestion one of the most serious problems that limits the physical implementation of chips.Based on the company's projects,this paper completed a back-end design of a sub-module of a 7nm high-performance graphics chip.The results achieved by the thesis are as follows:1)This thesis completed the FloorPlan,Place,CTS and Route of the sub-module.This thesis studies the design guidelines of the 7nm process,analyzes the data flow between different modules in the block,and determines the macros'location.In the floorplan stage,the placement of macro,power planning,and insertion of physical cells are completed.In the stage of placement,according to the timing and congestion estimation,the corresponding constraints are set and the standard cells are placed.At the same time,the timing and congestion results are improved,and the scan chain reorder is performed to reduce the unreasonable allocation of the routing resources.During the Clock Tree Synthesis(CTS),the common clock tree structures and the performance evaluation parameters of the clock tree are studied.Moreover,this thesis finishes the CTS flow with a low-power technology,clock gating;the flow of the routing is also introduced;When the routing is completed,this project introduces the physical rules check,together with formality and layout versus schematic,also presents the static timing analysis(STA)used in timing analyzing for nanometer design.Meanwhile,DFM(Design For Manufacture)is performed to increase the chip yield;2)This thesis fixed timing violation,DRC and DRV.Based on final timing and DRC reports,this paper studies the reasons for these violations,tries to fix these violations by changing the floorplan,adding placement constraints and some other methods;In the ECO phase,different kinds of violations,such as timing violations,physical rule violations and design rule violations(DRV)are analyzed,and the related fixing methods are presented.3)This thesis evaluated the effect of the new technology on the back-end design and used a new OCV model for timing analysis.For the new problems faced by the new deep nanometer technology,this paper discusses a novel technology,double pattern technology,the new spacing requirements of this new technology,and the impact of this new process on the back-end design flow.Since the technology has developed to the nanometer level,the normal on chip variation(OCV)method used in the past is too simple and too pessimistic.This thesis introduces the more advanced AOCV and the POCV model used in this project to refine timing analyzing with process variation taken into account.According to the final results,the maximum frequency of the module is up to 2.0GHz,and the scale is 1.7 million gates.The size is 559,099.3565?m~2(1,030.3320?m×542.6400?m),reached the sign-off requirements.Through the research of this thesis,it provides new solutions for the timing and congestion problems faced by the back-end design in deep nanometer technology node,and provides some support for the development of the domestic integrated circuit back-end design.