Facing To Paralle Program Of DMA Module Design On High Access Efficiency

Recently,with the development of Integrated Circuit,integrated circuit technique size are changing,it becomes smaller and smaller,from 350 nm to 180 nm,even 28 nm,now,the size can reach the lowest,7nm.The integration level of chip becomes more and more higher,this situation results from the development of techniques and technology,the speed of the processor can speed up about 60% every year,but the bandwidth of the on-chip memory bank just increases 10% every year.The speed of memory bank is much slower than processor,and this situation influences the calculating speed of the processor,meanwhile,the memory bank becomes the limitation of the processor.What's more,integrated circuit technique size become lower,the Moore's law loses its influence,if we want to improve the speed of processor,we won't depend on the way of reduce integrated circuit technique size.At this moment,the architecture of chip and the bandwidth of data play an important role in the situation,therefore,the transmission bandwidth of data's increase will improve the calculate speed of processor vastly.There are many factors in modern memory accessing strategy,such as Data Cache,DMA and so on.The Data Cache mainly uses in the data exchange of the on-chip memory,nevertheless,the DMA uses in the data exchange of the off-chip and on-chip memory.This thesis mainly researches the transmission mode of DMA.There are many transmission modes in DMA,with the different transmission mode,with the different transmission data bandwidth.Therefore,if we design and use the suitable transmission mode,we will improve the advantages,for example,reduce the transmission delay,add the transmission bandwidth and advance the property of memory bank.This paper introduces some aspects of the DMA,including transmission design and verification on the basis of GPDSP project in National University of Defense Technology.There are four parts in this paper:First,this paper introduces the structure of off-chip memory,analyzes the accessing flow of memory bank,discusses the chip structure of GPDSP and the transmittal mode of traditional DMA.Meanwhile,the author researches that the flowing process of DMA,and DMA influences the data flitting.Second,according to the trait of parallel program,the author designed various special transmission mode,including data scattering transmission,broadcast transmission,data merge transmission,what's more,according to the benchmark test program of different data scale and data shape configuration,the author compared the data bandwidth,DRAM hit rate under the DMA common transmission mode and special mode,even,the author summarized the rule,that is bandwidth increased 85%.Third,according to the need of the GPDSP project,it includes compatibility AXI standard protocol trunk,the thesis introduces the trait and structure of the AXI protocol,designs DMA-AXI bridge module.The DMA-AXI bridge consists of DMA-AXI master bridge,DMA-AXI slave bridge and DMA-AXI arbiter.Fourth,according to the mode of module level verified,the author confirmed the verification plan,designed input encouragement,set up UVM verification testbench,meanwhile,the author verified all the function points to the DMA-AXI bridge module,made the function fraction of coverage achieved 100%,coding coverage rate can be explained 100%,and the data satisfied the request of indicative.In the DC integrated environment,the author used the TSMC 40 nm process database,and synthesized the DMA-AXI bridge.At last,the thesis synthesizes many factors,including timing,area and power consumption,all these factors satisfied the request of indicative.