Neural Activity Correlation Processor: Reduced Transmission Bandwidth Using Linear Estimation

In implantable brain activity recorders, the bandwidth of transmission is constrained by a limited power budget. Simultaneously, the amount of raw data gathered from the brain environment is relatively large. Therefore, an effective information extraction algorithm is required. In this dissertation we develop a new data compression algorithm which is adjusted based on the limitations mentioned.;State-of-the-art implantable neural signal recorders use pattern recognition for information extraction. However, the raw signal recorded on most of the probes is a superposition of many action potentials. This is mainly due to the probe design and to the density of brain neurons. In current information extraction methods, the signals from probes with detectable action potentials are used and the signals from remaining probes are discarded.;The main source of redundancy in recorded analog signals is crosstalk noise resulting from a neuron coupled to more than one probe. Our first contribution is to develop a low-power analog preprocessor which removes this type of redundancy. Minimizing redundancy reduces the transmission bit-rate for commonly used encoding methods. Consequently, this preprocessor opens the road for incorporating many well-developed encoding algorithms without sacrificing efficiency. For example, the activity of a single neuron will appear in only one of the channels, decreasing the number of clusters developed during the learning phase of information extraction in the recognition algorithm.;One method of signal compression for two closely correlated signals is to predict one signal from the other, for example using the linear minimum mean square error (MMSE) estimator. The error can then be defined as a new signal. Our second advance is to devise a novel, hardware-efficient, gradient-descent-based method of deriving the MMSE estimate for four signals from adjacent probes. The estimator is then used to reduce the information embedded in the signal, decreasing the bandwidth of the Analog to Digital Converter and the transmitter in the next level of design. Two prototypes of the design were successfully implemented and tested using discrete components. Finally equivalent sub-threshold component were designed and implemented in 0.13um IBM-CMRF process.