Research On Flying-adder For PLL

Phase-locked loop circuit is the most widely used in frequency synthesis technology.Its design and optimization are still hot topics.The Flying-Adder circuit architecture,based on an emerging frequency definition method,is a working circuit of a direct digital cycle synthesis technology.This thesis research on Flying-Adder for PLL.The direct digital cycle synthesis technology takes the time average frequency method as the theoretical basis and the Flying-Adder architecture as the working circuit.From the analysis of the method of time-averaged frequency,the Flying-Adder circuit has flexibly control for frequency,and has a capability of rapid frequency conversion because of that it is an alldigital open-loop circuit.In order to analyze the actual performance of the Flying-Adder circuit,a full-digital Flying-Adder basic circuit is simulated based on the theory of the direct digital cycle synthesis technique.The time-domain and frequency spectrum analysis are used to obtain the frequency control word.Range and corresponding output frequency,and analyze its performance from the frequency synthesizer performance index.For the nonideal factors of multi-bit transitions and insufficient operation speeds of accumulators in the Flying-Adder basic operating circuit,this paper proposes the use of the two-way interlock circuit,which is different from the basic circuit.For the non-ideal output of the Flying-Adder circuit,this paper proposes a method to remove the spurious signal at the cost of reducing the frequency,and provides more space for the Flying-Adder circuit.Based on the analysis and design of PLL circuit,the application of Flying-Adder circuit in PLL circuit is studied.For applications,analysis is performed from inside the ring and outside the ring.For out-of-loop applications,the phase-locked loop provides input reference signals for the Flying-Adder circuit.The good frequency purity of the phase-locked loop ensures the accuracy of the output of the Flying-Adder circuit,and its output frequency range is expanded by Flying-Adder circuit,the actual frequency of up to K/2 times the original frequency.For the in-loop application,the Flying-Adder circuit is used as a frequency divider in the phase-locked loop.Compared with the integer frequency division,the frequency resolution is improved,and the fractional frequency division effect is achieved from the arrival,and is different from the fractional frequency division ratio.Yes,it does not produce fractional spurs.By analyzing the application of Circuit inside and outside of the Circuit of the Flying-Adder,this paper proposes a FAPLL circuit structure,which can control the output frequency through four frequency control parameters.Compared with the original PLL,it has a larger frequency range and a higher frequency.Frequency resolution.Based on the SIMC 0.18?m process,the circuit is constructed and simulated on the Virtuoso platform.It can be seen from the simulation results that the frequency tuning range of the PLL is from 100 MHz to 660 MHz and the minimum frequency resolution is 1.25 MHz.For the whole FAPLL,the frequency can reach up to 1.32 GHz,and the lowest can reach 781.25 k Hz,and the output is a periodic stable square wave signal.When the system allows the TAF clock signal,the integer frequency divider can be removed.At this time,the output frequency can reach up to 2.64 GHz,and the lowest frequency can reach 50 MHz,and due to the advantage of the TAF clock,any value can be taken in this tuning range.The use of an FA circuit greatly improves the frequency range of the original phase locked loop circuit and has a high frequency resolution.This article also analyzes the Flying-Adder circuit under the mismatch of VCO.Under the mismatch of VCO,the output frequency of Flying-Adder circuit does not change,and in the case of integer divider,the spurious signal can be removed or even completely eliminated.For the FAPLL circuit,it can maintain a relatively good output.