Research&Design Of The Low-noise Frequency Synthesizer

The wireless market has experienced an exponential growth over the past decade.To sustain this growth and increasing demands of new wireless standards,the cost,battery lifetime,and performance of wireless devices must all be enhanced.One of the most critical components in a wireless transceiver is the frequency synthesizer.With the advancement of radio frequency(RF)technology and requirement of low noise?power,new RF architectures are needed.A phase locked loop is a typical example of a frequency synthesizer.In this thesis simple low noise?power phase locked loops are designed and implemented for analog systems.The paper analyzes the loop transmission characteristics of the PLL,the stability of the loop and the performance of the circuit.Then the contribution of each module noise to the loop noise is analyzed.In this paper,two types of voltage-controlled oscillators are designed.One is a CMOS LC voltage-controlled oscillator based on a self-biasing linear trans-conductance technique.The NMOS and PMOS switching transistors reduce the power consumption.In realizing the Smaller chip area,eliminating RF choke inductor is essential for the LC choke inductance of the single-ended NMOS or PMOS;on the other hand,the capacitive feedback improves the oscillation amplitude and reduces the LC loop load through the capacitive feedback from the drain of the MOS device to the LC resonant circuit,Computation and simulation prove its superior phase noise performance.The achieved figure-of-merit with tuning range(FoMT)from 196.5 to 199.5 dBc/Hz.The other is a ring oscillator with a differential structure.The voltage controlled oscillator of the structure is composed of a self-biased structure and a symmetrical load delay unit,which effectively restrain common mode noise,reduce power supply fluctuations and external disturbances on the voltage controlled oscillator the effect of noise is that the output differential signal is converted to a 50%duty cycle clock signal by the buffer unit.Simulation results show that the voltage-controlled oscillator has generates the lower phase noise and meets the performance requirements of the phase-locked loop.Finally using matlab simulation to verify the stability of the system.The proposed PLL is fabricated and measured with a 0.18?m CMOS process.The core chip area is 0.24 mm2.The measured PLL frequency ranges from 0.13 to 1GHz,the phase noise at 1 MHz offset is from-85.1 to-89.4 dBc/Hz,with a power dissipation from 2.8 to 8.6 mW under a 1.8 V supply voltage across the frequency tuning range.The lockdown time for each operating frequency is less than 50?s.