Design And Research On EMMC Host Controller

With the intensification of the security market's high-definition trend,the security chip's requirements for the speed and capacity of external memory are also increasing.With the advantages of large capacity,high speed,ease of use,and high security,eMMC has become the first choice for security chip external storage upgrades.The development of eMMC host controllers has also become the focus in the industry.At present,the design and implementation of the eMMC host controller in the field of security chips is still lagging behind,especially in terms of support for the eMMC 5.1 specification.This paper aims at the actual application requirements,researches and designs an eMMC host controller based on AMBA 3.0 bus,which conforms to the eMMC 5.1 protocol specification and is integrated in the security monitoring chip.It is used to realize the communication between the SoC and the eMMC device,satisfying the need for real-time storage of large-capacity high-definition video data by security monitoring chips.It is of great significance for designing high-performance SoC and enhancing the external storage performance of the system.The eMMC,APB,and AXI protocols are thoroughly studied to achieve the best performance,compatibility,and robustness of the design.The eMMC host controller fully supports the eMMC 5.1 protocol.The main innovations include:(1)Based on the new features of the eMMC 5.1 protocol,command queuing is implemented on the hardware,which helps to improve the performance of frequent fragmented access operations.(2)An automatic command register is set in the controller,which can automatically start the sending of the next command after completion of one command.It simplifies the sending of commonly used combination commands in the eMMC protocol.(3)For the characteristics of eMMC data transmission,the controller externally uses two 512-byte single-port RAMs as data buffers,and uses ping-pong operation to reduce the data transmission delay.The RTL code has passed comprehensive and rigorous functional verification to ensure the correctness and feasibility of the function.The synthesis results show that the total area is118670.808052μm~2 based on TSMC 90nm CMOS technology.After static timing analysis,the module operating clock successfully reaches the target frequency of 400 MHz.This design has achieved good performance in terms of function,area,and timing.It can give full play to the outstanding features of eMMC 5.1 and improve the external memory performance of the security chip.