Study On The Design Of NFC Passive RFID Tag Integrated Circuit

Near Field Communication(NFC)is a short-range high frequency radio technology that is evolved from non-contact radio frequency identification(RFID)technology integrated with interconnection and interworking.It is able to identify and exchange data with compatible devices within a short distance.NFC has many advantages such as low power consumption,high security,and fast transmission.With the rapid development of the Internet of Things and e-commerce,NFC is widely used in devices that support NFC technology,such as mobile terminals.In this thesis,we studied and designed a digital baseband of a ultra light weight electronic tag chip for NFC application.The IP core of the tag chip is designed independently by Verilog HDL language.In accordance with the principles of composition and knowledge of NFC tag system,this paper has a detailed research on NFC protocol standard technology such as communication mode,modulation type,coding technology,frame structure,CRC check,anti collision loop,data communication and so on.Then,the system architecture of digital baseband has been designed and planned according to the design goals,using the top-down design method.The core technology problems such as the distribution of clock planning,the incompleteness of working clock,the coordinated operation of modules,the parsing of instructions,and the access of NDEF files have been studied in detail,and standardized designs have been made.Secondly,according to the functions of each module and time sequence,we design each module using the down-top design method and simulate the function of each module to verify the function of each module.Thirdly,after interacting with each sub module,we simulate the whole system to ensure the correct operation of each module,and analyze the completeness and feasibility of the design.Fourthly,in order to improve the probability of the one-time tape out success,we write the digital baseband into the FPGA and build a complete NFC tag by combining FPGA with the Analog front-end set up by discrete components.The accuracy of the digital baseband IP is verified by the communication tests with the mobile NFC.Finally,the digital baseband of the NFC tag is physically implemented using the Design Compiler tool of Synopsys company based on the 0.18?m CMOS process of Global Foundry.According to the synthesized netlist using Synopsys SOC Astro tools to generate digital module layout and taped out.The area is only 750?m x 950?m(contains Pads).Through the test of the chip,the functional requirements of the design are realized,and the power consumption is 70?w.The result of the test has reached the design goal of this thesis.