Research On Low-power Short-range FSK Transceivers

With rapid development and extensive application of wireless connectivity,the energy efficiency and the spectrum efficiency of the transceiver become critical in modern short-range communication systems.With advanced CMOS technology,the wireless transceiver consumes most power,and the receiver front end circuits often become a bottleneck in the design of the ultra-low power(ULP)transceivers.In this thesis,a low power 2.4 GHz receiver front end with wideband frequency shift keying(FSK)modulation and a two-point modulation fractional-N phase-locked-loop(PLL)are designed in 65 nm CMOS.To avoid the image-rejection problem in the conventional heterodyne receiver as well as the DC offset and LO leakage problems of the direct conversion receiver,a sliding-IF architecture is chosen for simple hardware implementation.In addition,a low voltage fractional-N hybrid PLL based on two-point modulation is designed for the transmitter.The PLL can also be reconfigurable for the LO generation in the receiver.The receiver front end circuits including the LO generation PLL consume 2.4 mW from a 0.8 V supply.An energy efficiency of 0.24 nJ/bit and a sensitivity of-89 dBm could be achieved,respectively.Besides,a frequency-domain OOK(F-OOK)modulation transmitter is proposed with a phase rotator and a 4-stage ring digital/voltage-controlled oscillator(D/VCO)to achieve high energy,bandwidth and area efficiencies.Both frequency deviation and frequency modulation are realized in the phase domain by utilizing the phase rotator.A 9-bit phase rotator covering a phase shifting range of 180° is designed with a phase resolution of 5.625° and phase steps of 32.A hybrid 2.4 GHz PLL with a 4-stage ring D/VCO generates orthogonal signals as inputs of the phase rotator.The proposed F-OOK transmitter designed in 65 nm CMOS consumes 5.4 mW from a 1 V supply at the maximum data rate of 10 Mb/s,achieving an energy efficiency of 0.54 nJ/bit.