Study On Die-shift Of Fan-out Wafer Level Package

Fan-out wafer level package(FOWLP)has stable chip units,high integration,high reliability,good mechanical protection,larger package area,and higher cost performance,and has become the current IC chip package.The mainstream technology.Although products based on FOWLP technology,such as processors,sensors,communication modules,etc.,occupy an important position in the IC market,many challenges still faced by the technology,such as the accuracy of line patterns and vias,the choice of connection methods,The realization of 3D packaging and the choice of different packaging processes.This article first reviews the current development of fan-out packages.By dissecting the commercially available electronic packaging products,the deficiencies of the current four major packaging technologies and their packaged products are analyzed.In order to solve the problem of chip migration,research is being conducted on technologies such as chip redistribution,plastic encapsulation,and rewiring,which are closely related to it.The ANSYS finite element analysis software was used to model the die offset and warpage problems by modeling solid modeling,meshing,and applying loads to complete the product's overall model,and the offset generated by thermal expansion and the warping of individual grids.Curvature was calculated,and finally the main reason for the chip offset was obtained through simulation.On this basis,combined with the existing process conditions,a proposal was made to improve the shape of the double-sided adhesive film on the edge of the chip.Based on this,the feasibility of the scheme is further verified by experiments.Finally,the packaged product was tested and examined from the perspective of appearance inspection,solder ball strength testing,and overall electrical and thermal properties.The results show that the improved packaging process is stable and reliable,and the total chip offset can be less than 5um,the total warpage less than 3%,the appearance inspection index,the quality of the solder balls and the electrical performance are all in compliance with the requirements.The product's total yield rate is higher than 80%.Compared with the existing technology and process flow,this solution can solve the chip offset problem and verify the improvement and process feasibility.