Board-level Reliability Research And Simulation Of Large Size Wafer-level Fan-out Packaging

Since the 21 st century,the emergence of various consumer electronics has promoted the development of wafer-level packaging technology.Fan-out packaging has attracted more and more attention with its excellent characteristics and is widely used in various chips.In the next few years,the market size of fan-out packaging is expected to increase to US$3.8billion.With the development of new technologies such as the Io T,5G,AI&VR,and automotive electronics,the demand for high-density and multi-chip integrated packaging technology is becoming increasingly urgent.The application of fan-out packaging will also develop towards more chip integration and larger size solutions.However,large-size packages face many challenges in the development and application process,which severely restricts mass production.In addition,the reliability of a large-size package directly determines its feasibility in practical applications.Therefore,it is necessary to evaluate the hidden risk points and failure problems in the package,and to further improve the reliability to meet its application requirements.In this subject,large-size embedded silicon fan-out packaging(e Si FO)is studied.The technology uses a silicon-based fan-out structure to replace the molding compound in the classic fan-out package to provide fan-out space for the redistribution layer and solder balls.The process is simple and the performance is excellent.In the in-depth study of the key processes in the large-size packaging,combining the theory with the experiment,we proposed the optimization plan of the large-size groove etching process and the die attached process.Reliability research was conducted from two aspects such as package-level reliability and board-level temperature cycle reliability.Firstly,we conducted package-level reliability experiments on the test samples,and then carried out experiments and simulation analysis to provide solutions for cracks in the dry film after temperature cycling test and delamination of the passivation layer after high accelerated stress test.Secondly,we used finite element simulation analysis to explore the response of products with different packaging structures under board-level temperature cycling conditions,and to further explore the impact of different PCB thickness and chip size on the fatigue life of solder balls,so as to optimize the design and provide a reference for the reliability evaluation and design of the actual product.