| The chip packaging requirements (e.g. technical performance, physical specifications, and manufacturing costs) up to year 2014 are distinctly spelled out in the International Technology Roadmap for Semiconductors (ITRS) prepared by the semiconductor industry for six different technology sectors: low-cost, hand-held, cost-performance, high-performance, automotive and memory. A novel Compliant Wafer Level Package (CWLP) technology is developed to address the chip packaging requirements beyond 2014 and to introduce innovative design and fabrication concepts that will further advance the technical performance of the chip, the package, and the system board. The CWLP process technology simultaneously packages all of the integrated circuits (ICs) intact in wafer form. This produces a wafer-at-a-time packaging process instead of an IC-at-a-time. The CWLP provides the ability to assemble the packaged parts on the system board without the use of underfill materials and to conduct advanced analog/digital testing, reliability testing, and burn-in at wafer level. The fabrication process of a CWLP prototype, a high density CWLP, and a high density CWLP with embedded air gaps is discussed and the electrical, mechanical, and thermal characteristics of the CWLP are described based on the results of physical simulations and experimental measurements. A novel set of analytic models is created to investigate the unique advantages of the CWLP technology in terms of the maximum number of input/output (I/O) connections, high packing density, superior electrical, mechanical, and thermal performance, ease of integration with the semiconductor and the system board manufacturing processes, and low manufacturing cost. |
