Design Of High-performance Floating-point DSP Coprocessor

The AVP335 is a 32-bit high-performance floating-point digital signal processor(DSP)with very rich on-chip peripherals and a large amount of on-chip memory,whose floating-point processing unit(FPU)has very powerful capabilities in numerical computation and processing.Co-processor is a chip designed for certain applications whose data is processed slowly or incaplable to be dealt by the CPU.It is mainly used to assist the CPU in the processing of these specific tasks such as floating-point operations,calculations of transcendental functions and so on.Therefore,the coprocessor is designed for a specific application,not for a general-purpose processor.A 32-bit high-performance floating-point DSP co-processor is designed in this research,which is mainly used to assist the CPU in calculating and processing the numerical value of floating-point numbers.According to the basic functions and design requirements of the coprocessor,the composition of the coprocessor is firstly introduced,including floating-point standards,registers,pipelines,instruction sets,and addressing modes.Secondly,the numerical calculation unit of FPU has been analyzed and designed in this research,mainly including the research of algorithms such as adder,multiplier and divider.In addition,further improvements have been made to the corresponding algorithms in order to achieve better performance of the numerical computing unit.Therefore,the design of the adder is implemented by the improved Two-Path algorithm,In other words,it can be performed by reducing the shift operation in the operation path and increasing the parallelism of the path.The multiplier can be performed by base 4 Booth algorithm to encode the multiplier,reducing the number of partial products,and then using the Wallace tree compressor to complete the partial product compression,and completing the final addition based on retaining the carry adder(CSA).Base 4 SRT algorithm is adopted in the divider.Finally,the decoding control unit is designed in this research.In the part,the floating point instructions and the instruction execution process are first analyzed in detail,and then the instruction decoder is designed.After completing the design of each functional module of the FPU,the RTL code of each function module was written,and the verification of each function of the FPU was completed by adopting VCS and Ncverilog simulation tools.The simulation results show that the logic design of the processor is completely correct and reasonable.In the end,the co-processor system is simulated and verified in a semi-customized way based on a 0.13 ?m CMOS process.