The Low Latency Of Data Transmission Design Based On FPGA

With the emergence of 10-Gigabit Ethernet,the massive transfer data in the optical fiber has a great pressure on financial trading system which requires real-time processing.The traditional way of software or software as the core in the hardware accelerated method can`t meet the low latency of transport demand in the trading system.Therefore,we urgently need to find a solution to meet the real-time processing in the trading system.Through access to relevant information,I found that a method is effective and easy to implement by adopting the hardware acceleration program.Considering the trading system requires continuous improvement for time operation,take a high speed and configurable acceleration scheme is the key to solve the problem.When considering the design,this article regards the process which the network card receives packets until the valid data be put into the host memory as a prototype.This article uses a simplified hardware design scheme to release the process of TCP/IP protocol stack and encryption arithmetic which take up a lot of time from the operation of the processor,and achieve the process by hardware platform,in order to achieve the low latency of data transmission.In the end,this articles use the actual test results verify the rationality of the design.According to the above assumptions,this article proposes a hardware acceleration scheme which the TCP/IP protocol stack and encryption arithmetic process are realized on FPGA,and the transmission between server and FPGA is realized by using highspeed bus technology.In addition,the TCP/IP protocol is implemented by TOE,the encryption algorithm using DES algorithm to design,and the high-speed transmission adopts the PCI-E bus.The design adopts Vivado as the integrated development environment,and adopts Modelsim as the waveform simulation tool.Test results show that the rate of DES encryption algorithm implementation by hardware can reach 16 Gbps,and the delay of DES module is 64 ns.The rate of DMA read and write are 318MB/s and 476MB/s,and the delay of PCI-E module is 750 ns,the delay of TOE is 190 ns.Therefore,the total delay of system is 1.1us,and the power consumption of the whole system is 2.926 watts.Compared with the software solutions,hardware has a larger advantage in power consumption and latency,which has a good application prospect.