Low Latency Ad Hoc Network Design And Implementation Based On FPGA

Compared to the traditional centralized wireless network with base station and mobile device, wireless Ad hoc network is composed by equal peers. Wireless Ad hoc network has become an important branch of wireless communication technology, because it is more flexible, more robust than traditional wireless network, and can construct network independently. Normally, Wireless Ad hoc network uses CSMA/CA or TDMA protocol to access the media, which results in large end to end transmission latency. Therefore, Wireless Ad hoc network using CSMA/CA or TDMA protocol is not applicable for low latency scenario, like military communication.To solve this problem, based on the Ethernet interface and the physical communication link, this thesis has designed a media access and network construction protocol combined competition and TDMA method, and implemented on FPGA. Meanwhile, this thesis has also designed and implemented a high precision global time synchronization protocol. The main contribution of this thesis are as follows:Firstly, this thesis has discussed normally used media access protocols and time synchronization algorithms, and detailed design target based on application scenario and implementation constraints.Secondly, based on design target, this thesis has designed the low letancy Ad hoc network layer, which divided into broadcast channel, user data channel and receving and transmitting switching module, used for network construction, IP-based user data transmission and TDD media access control respectively.Then, this thesis has discussed implementation details based on FPGA by submodules, including state machine transformation, coding and decoding frames procedure, receving and transmitting switching control and so on.Finally, the implemented network layer combined with physical layer has been tested under AD/DA loopback and wireless transmission scenario. The results have shown that the whole link combined with network layer and physical layer can achieve minimum 4.5ms end to end latency in the distance of 100 km, with 6.4Mbps maximum user transmission bandwidth, and can achieve 4ns time synchronization precision.This thesis has provided a low latency solution for wireless Ad hoc network based on FPGA, which is highly extensible, and is applicable in low latency application scenario.