Design And Implementation Of Configurable Efficient Coding And Decoding IP Cores For LDPC Codes

Rate-compatible LDPC codes are becoming the preferred choice of channel coding schemes in various communication systems due to their excellent error correction performance and compatibility with time-varying channels compatible with multi-rates.Papers focus on the research of LDPC code rate compatible and low resource consumption of hardware.After understanding the basic principles of LDPC codes,a parity check matrix that is compatible with multiple code rates and multiple code lengths is constructed.Based on this,a design and implementation of an LDPC codec and IP core encapsulation are achieved,resulting in good usability,reusable,high correct codec.First of all,aiming at the situation that the multi-rate compatible LDPC codes occupy high hardware resources,several commonly used code rate-compatible implementation methods are studied.By using the extended matrix method and the improved quasi-cyclic check matrix construction method proposed in the paper,constructed to be compatible with four kinds of code rate and two kinds of information frame length check matrix.Then,based on the several parity check matrices constructed in this paper,through studying the encoding algorithm of LDPC codes,proposed an improved iterative algorithm based on quasi-cycle,and realized the FPGA design and further optimization of its algorithm structure.Compared with the direct encoding method has been greatly improved resource occupancy.Next,the algorithm of LDPC decoding based on belief propagation and several improved algorithms are deeply studied,and the design and implementation of FPGA for the decoder are realized according to the paper.Finally,aiming at the difficulty of hardware implementation of LDPC code decoding algorithm,the high complexity of the algorithm description and the long development cycle,the thesis proposes a method to synthesize LDPC code decoder design using high-level synthesis tools.The method uses high-level language to describe the complex algorithms and optimizes the algorithm through hardware adaptive modification and adding constraints,and then uses the high-level synthesis tool to convert it into RTL code.After full functional verification,the algorithm module output in the form of IP core.The high-level integrated implementation of LDPC code decoding algorithm not only reduces the difficulty of algorithm hardware development and greatly shortens the development cycle while ensuring the performance of the decoder.