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Analysis And Design Of High Performance 32-bit DSP Core

Posted on:2019-11-24Degree:MasterType:Thesis
Country:ChinaCandidate:X Y WuFull Text:PDF
GTID:2428330548482386Subject:Electronic Science and Technology
Abstract/Summary:
DSP(Digital Signal Processor)chip is particularly suitable for digital signal processing and is commonly used in control of industrial intelligent or hand-held devices,Fourier transform of digital signals,convolution operation and audio and video signal processing,etc.The application of DSP chip is getting wider and wider.This paper has completed the analysis and design of a 32-bit high-performance digital signal processor DSP core.From the design of its architecture,this paper carries out detailed analysis on its bus architecture,DSP overall composition,the division of the pipeline structure and its series,the instruction system design and the definition of the addressing modes and other architecture information.The kernel is designed from its addressing unit module,the design of the instruction register IR,the arithmetic logic unit ALU,and of the instruction decoding unit.As for the design of arithmetic logic unit,the adder,the barrel shifter design and the multiplier are introduced in detail in this paper.After the the completion of the basic design,the whole chip is verified by functional simulation at two levels of modularization and system level.The arithmetic logic unit in the kernel is mainly based on the modular verification strategy,for instruction decoding unit,addressing mode.The verification of the instruction register module IR is mainly based on the system-level strategy.Based on the Ncverilog simulation platform,this paper aims to build the corresponding simulation environment,write the test bench file,configure the related GPIO,and compile the corresponding machine code as the simulation excitation signal based on the definition of the instruction set.From the simulation waveform,the correctness of the function of each module in the kernel can be seen clearly.After the functional verification was passed,Synopsys's Design Compiler synthesis tool is used to comprehensively optimize the designed code,and the gate-level netlist and sdf file corresponding to the target technology library were obtained,besides,the post-imitation has been completed.After a series of work,such as layout and wiring,the chip is taped out and physical tests were carried out after tape-out,thus the correctness of DSP system design can be seen from the test results.
Keywords/Search Tags:Harvard Bus, DSP Architecture, ALU, Timing constraints
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