Research And Design Of 3-5GHz RF Receiver Front-end Chip

In this thesis,a RF receiver front-end chip that operates at 3-5GHz is designed for 5G communication.The RF receiver front-end consists of two main modules:a low noise amplifier(LNA)and a passive down-conversion mixer.The design specifications of each module and the overall front-end are clarified and all circuits have been completed.According to the requirements of the area,the low noise amplifier in this thesis must adopt inductorless structure and have the function of single-to-differential.After comprehensively analyzing and comparing several structures,the low-noise amplifier in this thesis is based on the common-gate common-source noise-cancelling structure to ensure low noise and single-to-differential.In addition,LN A in this thesis introduces feed-forward technique to reduce the power consumption and noise contribution of common gate stage.It also adopts current-reusing technique to increase the gain.Besides,a cross-coupled balance buffer is added at the output of the LNA to improve the differential performanceThe mixer in this thesis adopts a current-driven passive downconversion mixer structure.The main modules include passive switch pairs,fully differential transimpedance amplifiers and the local oscillator(LO)chain.Passive switch pairs have no DC power consumption and flicker noise is small.Transimpedance amplifier uses a common gate structure.Compared to the traditional transimpedance amplifier implemented by operational amplifier,common gate structure is more stable and can provide wider IF bandwidth.The LO chains include a divide-by-two divider,AND gate and buffer circuit.The main purpose of the LO chain is to convert the differential input sinusoidal signal into a quadrature 25%duty cycle output signal to drive the passive switch pairs.Compared to the 50%duty cycle LO signal,the 25%duty cycle LO signal offers greater conversion gain and better noise and linearity performance.Considering the great impacts that layout has on the performance of the RF circuit,this thesis gives the the flow chart and basic principles of layout design,especially focusing on the layout design of the RF receiver front-end.The RF front-end chip is finally completed using TSMC 65nm CMOS process technology.Under the supply voltage of IV,the simulation results show that S11<-10dB and noise figure(NF)<3.8dB at high gain model and NF<5.6dB at low gain model.The conversion gain is adjustable and greater than 27dB.The IF bandwidth is greater than 200MHz.IP1dB>-28dBm at high gain model and IP1dB>-24dBm at low gain model.IIP3>-19dBm at high gain model and IIP3>-15dBm at low gain model.