Research And Design Of A Key Technology For Accelerating Convolution Computation Based On FPGA

With the development of Internet technology,deep learning has brought a positive cycle of artificial intelligence,and traditional computing architectures have been unable to support the demand for massively parallel computing.Therefore,it is necessary to shorten the training time of the deep learning algorithm by accelerating the calculation process of the underlying application,thereby promoting the development of the entire industrial chain of artificial intelligence.Convolutional Neural Network(CNN)is an important network model for deep learning algorithms.It has a wide range of applications in the field of handwriting recognition,natural language processing,medical image segmentation,etc.It is also a hot topic in machine learning,computer image vision and other disciplines,and therefore has certain research significance and value.The convolutional neural network requires comprehensive evaluation of all regions in the feature map,so it has a large computational complexity.In its training process,since the data information is stored and processed by each neuron,the convolutional neural network can be parallelized,so that training data and training parameters can be updated at the same time.In order to speed up the calculation process during training and reduce the training time of the algorithm,it is considered to use hardware and software technology to implement the convolutional neural network in parallel instead of the traditional serial calculation method.Therefore,this paper first proposes a simple convolutional neural network model--SpNet model,and analyzes the different types of parallelism in the convolutional neural network training process in detail.From the point of view of software and hardware,the calculations are designed to speed up the calculation of convolution calculations.Among them,the software program is: first convert the convolution calculation to matrix multiplication,and study the optimization algorithm of matrix multiplication.Secondly,propose a matrix multiplication algorithm suitablefor the convolution calculation in the model.Through experimental comparison,it can be obtained.A plan for accelerating the calculation of convolutions.The hardware scheme is: Based on the FPGA,the overall training architecture of the convolutional neural network model is designed,and the convolutional calculation module is designed and implemented in detail.Since the circuit itself is parallel,the hardware implementation can obtain an accelerated volume.Product calculation scheme.