| Adaptive Digital Beam Forming(ADBF)plays an important role in the field of gigital signal processing.With the growing popularity of ADBF algorithm,it's required to have high throughput,high precision,strong real-time and good universality in different application areas,such as Radar Signal Processing and Information Communication technology,etc.Compared to microprocessor(MCU),signal processor(DSP),and application-specific integrated circuit(ASIC),Field Programmable Gate Array(FPGA)has the characteristics of high speed operation,high accuracy and flexibility,which makes it have obvious advantages in the ADBF Weight Calculation.This paper designs and implements a configurable ADBF weight calculation IP core based on FPGA.Through the research of different ADBF algorithms,an improved Cholesky decomposition-SMI algorithm(Cholesky-SMI)is chosen to design IP core,which effectively reduces the computational complexity and hardware implementation difficulty.The design in this thesis adopts the standard AXI-Stream protocol for each IP core.Meanwhile,the IP core developes a stream processing structure,including covariance matrix,matrix inversion,U-factor calculation and power vector calculation,etc.Besides,By configuring two static parameters,the maximum dimension MAX DIM and the data throughput rate THROUGHOUT RATE,on the top of the ADBF IP core,different hardware structures will be generated,which has strong versatility.The proposed IP core has been implemented on a Xilinx device Virtex-7 690 and co-simulated using Matlab and Modelsim softwares.The synthesis results show that the design can realize defferent passing rates of 1.166M-1.317Mbps and the maximum clock frequency can achieve above 200MHz,when the maximum dimension is equal to 16,so the IP core can meet the processing needs of current advanced radar systems. |
