Research On Design Method And Implementation Technology Of Digital Filter Used In Sigma-delta ADC

Sigma-Delta Analog-to-Digital Converter is a low speed,high precision ADC based on oversampling technology,which is widely used in various fields such as audio processing,wearable devices and sensors.It mainly uses the oversampling technology and the noise shaping technology of the modulator to push the quantization error of the conversion to the high frequency band.High-frequency noise is filtered by a digital decimation filter to achieve high resolution,high signal-to-noise ratio A/D conversion.The digital filter section mainly determines the rate of A/D conversion,the overall power consumption and area of the chip.Therefore,it is very necessary to study digital filters.This thesis studies the implementation of a digital part of a foreign Sigma-Delta ADC chip.The digital filter,clock circuit,digital interface and control circuit are mainly studied by using the method of reverse analysis.The design methods of digital filters at home and abroad are discussed firstly,as well as the basic implementation,the advantages and disadvantages of the digital filter.The reversal extraction of layouts has been done as well as the functional blocks has been extracted and a set of methods and theories have been put forward for the reversal analysis of digital integrated circuits during the analysis of digital circuits of the chip.Secondly,the chip's digital communication interface and control circuit were analyzed,the structure of the interface registers was extracted and analyzed as well as the communication simulation with the whole digital module was completed.The modulator structure was analyzed and the clock generating circuit module was extracted and simulated.Finally,the structure of the digital filter inside the digital circuit was extracted and analyzed combined with the action of the control circuit.The signal transfer function is deduced,and a multi-mode configuration CIC filter structure based on structure multiplexing and time division multiplexing design is proposed.The overall functionality of the chip was verified and the modulator was models through Verilog.Verification of multiple input signals in multiple modes was performed to the filter and the reliability and correctness of the filter was verified by these ways.After logic synthesis and placement and routing of traditional structure and improved CIC filter,the improved structure has reduced power consumption by 44.24 uW,and the layout area has been reduced by 24.2% compared with the traditional structure.This thesis accomplished the inverse extraction and simulation of the digital part of the chip through the reverse analysis of this Sigma-Delta ADC,a digital filter structure with a multiplexing structure in multiple update rate is proposed at the same time,which has a certain reference value for the future design of Sigma-Delta products.