Research Of The Key Technologies Of Virtual Digital Component Library Design

In teaching of the professional compulsory courses of the IT(Information and Technology)subject,e.g.,digital circuit,the indispensable experiment is the main teaching content,helping strengthen the student' ability to understand the fundamental knowledge and cultivate their application skills.Because the VEP(Virtual Experiment Platform)can address some education issues in university development,such as input cost,the update of devices and components,the time and space limitation,it has increasingly become one of the main alternatives.Whether the digital circuit VEP based on the simulation software like MultiSim,developed independently with the design schemes of the object-based components,circuit models and the component library,or the usage of VHDL(Very-High-Speed Integrated Circuit Hardware Description Language),there are still a series of problems,such as the software copyright limitation and the high learning cost.Therefore,the experiment teaching is incapable of well integrate into the classroom teaching,and the students cannot have an experimental environment for effective self-learning and skill training.Especially,due to the closure and difference of the components in different platforms,the components and components libraries cannot be shared among difference VEPs.As one of the core infrastructures of the VEP,whether the VCL(virtual component library)is easy to be added or not is crucially relevant to the VEP usability and ease of use.But the design of VDC model is the key technology of VCL design.According to the demands of the digital circuit VEP,in this thesis,we study some key issues of the VCL designing.(1)The digital logic chips are divided into two types,the combination of logic chips and the combination of logic chips with control.These components are abstracted and formal described based on the analysis of the static structure properties and functional properties.Then,a model of virtual digital component with consistency is designed.(2)Applying the model verification based on timed automata,the conversion model from the virtual digital component to the timed automata has been constructed.Additionally,the converted model has been simulated and verified by the UPPAAL,a tool for model verification.In this way,we prove that the reachability and deadlock-free of the equivalent virtual component model are satisfied.(3)According to analysis and study on VCL,we defined an extendable VCL model based on abstraction and formal description.And then,based on the Qt information delivery,QMVC and GraphicsView,a component model and a one-to-one mapping between the component model and its package form are designed.In addition,some visual digital components are also implemented.Finally,based on the proposed VCL,an experimental VEP is implemented to construct the electronic circuit with the component in the VCL and make a demonstration for the circuit.In this thesis,the proposed VDC model with consistency can simplify the design and implementation of VCL and improve the usability and the portability of VEP.The users with not strong programming ability can make a new virtual component and assemble the digital experiment circuit via simple property configuration.The VEP,designed based on the proposed VCL model,is easy to use and can decrease the study costs.As a light-weight VEP,in the teaching of theory course like digital logic,it could both to be used as the demonstration and to assist students do their experiment independently,helping improve the practical and innovative ability of students.