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Hardware Implementation And Improvement Of Joint Source And Channel Coding Based On Double Protograph LDPC

Posted on:2018-05-07Degree:MasterType:Thesis
Country:ChinaCandidate:C A ChenFull Text:PDF
GTID:2428330515455682Subject:Electronics and Communications Engineering
Abstract/Summary:PDF Full Text Request
Shannon's theorem is one of the core theories of information theory.Low-density parity-check(LDPC)codes have been found that the iterative decoding thresholds is close to the Shannon limit.According to Shannon's classical separation theorem,the source and channel coding can be optimized separately while still maintaining the optimality of the whole system.However,the theorem holds only under ideal conditions.Due to the limitations of the design of separation,joint source-channel coding(JSCC)schemes draw much attention for its good performance and high efficiency.An innovative JSCC scheme based on double protograph LDPC(DP-LDPC),which uses P-LDPC code as both source and channel codes,has been demonstrated to outperform the conventional structures.This thesis focus on hardware implementation and improvement of JSCC based on DP-LDPC codes.The first major research content of this thesis is the design of the joint source and channel encoder based on DP-LDPC codes.Through the incorporation of the source code and the channel code as a joint matrix,the encoder is reduced to a single encoder.Moreover,the quasi-cyclic expansion method is utilized to design the joint matrix with quasi-cyclic structure.Thus,the consumption of the hardware resources of the encoder is greatly reduced by the use of the shift register.Especially,the RAM resources are reduced by about 80 percent.The second main research content of this thesis is the design of the joint source and channel decoder based on DP-LDPC codes.An innovative decoding idea is utilized,where source code matrix and channel code matrix as well as the linking matrices are combined as a joint matrix for the joint system.Thereby,the proposed decoding scheme can simplify the design structure without increasing the complexity in hardware implementation.After describing and verifying the hardware architecture,the experimental results of the whole design for JSCC based on DP-LDPC codes over the additive white Gaussian noises(AWGN)is obtained.It can be found that it has the maximum gap of 0.2dB in comparison with the simulation results.
Keywords/Search Tags:Protograph Low Density Party Check, Quasi-cyclic Structure, Joint Source Channel Coding, FPGA
PDF Full Text Request
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