FPGA-Based Robust Intellectual Property Watermarking Algorithm At Physical Design Level

With the continuous development of VLSI system,people's demands for integrated system have been greatly improved.More and more logic functions are expected to be implemented on one silicon slice.Meanwhile,FPGA has gradually become mainstream technology in integrated circuit design.In development of FPGA-based designs,IP(Intellectual Property)reuse technology is adopted to risk for designing products and reduce shorten design cycle.Consequently,IP protection in reuse technology has become a key issue of common concerns for many research institutes and semiconductor companies.Digital cores multiplexing technology is the key to shorten the approved design cycle and reduce the cost of chip design.However,the practical application of this technology in the protection of intellectual property cores are often vulnerable to the threat of illegal attackers.Taking into account the design and development of a new FPGA cores circuit requires a lot of time and effort,in the process of reuse cores,the owner of cores do not always want to be illegally stolen.Therefore,FPGA-based IP watermarking technology as an effective means of copyright protection has become the industry's research focus.Firstly,this paper presents a robust IP watermarking algorithm based bitstream file,the algorithm is mainly determined by random sequence watermark position of embedding idle LUT,then using the LUT information table of bitstream file hide decentralized the different watermark information;when the watermark information needs to be extracted,we can extract watermark information by reconfigurable features of FPGA,the watermark information can be extracted sequentially from the LUT location of FPGA.Verify the results from the Virtex XCV600-6bg432 platform to show,to ensure the entire watermark core logic circuit function is not affected.Experimental results show that this algorithm is strongly robust and has low resource overhead.Then we propose a watermark embedding design method FPGA-based netlist level,we limit the dynamic addressing part of the logical table,thus releasing a look up table(LUT)for the insertion of the watermark information.As a result,we tightly integrate watermark information and logic functions,to prevent simply remove the tag to damage the intellectual property.Converting functional LUTs to LUT-based RAMs or shift registers prevents deletion due to optimization,in order to improve the robustness of the embedded watermark.The method be experimentally tested in Xilinx Virtex-Ⅱ environment.Experimental results show that the method in terms of resource overhead expenses low and good robustness.