Research On The Fault Tolerance And Parallel Simulation Of PCM Wear-Leveling Algorithms

As the poor scalabilit y of DRAM is gradually reaching the limitat ion,DRAM has been unable to meet the high performance computers' requirement for large capacit y memory.Phase Change Memory(PCM)has been widely concerned and studied for such advantages as nonvo lat ilit y,low stat ic power consumpt ion,high integration,byte-addressing,etc.Co mpared wit h other non-volatile storage material,PCM is beco ming a powerful co mpet itor to substitute DRAM and NAND Flash.However,on the one hand,so me deficiencies are st ill exist ing in PCM,such as limited write endurance,high write power and lo ng write latency.On the other hand,the great majorit y of PCM researchers have to experience a very lo ng experiment t ime when they use current PCM simulators to do their researches.LPCMsim is a light-weighted PCM simulator designed for wear-leveling and error correct ion study.The simulat ion speed of LPCMsim is st ill slow though it has been great ly improved co mpared to other simulators.Focused on low write endurance o f PCM and slow simulation speed of LPCMsim,the fo llowing research work are carried out.Wear-leveling is an effect ive way to lengthen the PCM write lifet ime.However,our analysis found that wear-leveling is likely to cause data po llut ion,that is,errors at a small number of blocks will be gradually enlarged and spread to the whole PCM space,thus to reduce PCM lifet ime and reliabilit y.To so lve the data po llut ion caused by wear-leveling,this paper proposes a method in whic h an bad block management mechanism(WLWO)is added to wear-leveling algorithms.WLWO reserves some space in PCM at first,when encountering a new bad block,WLWO replace s it with a free block fro m reserved space in order to prevent wear leveling algorithm fro m migrat ing the error-free data into bad block causing data po llut ion,thus to pro long the lifet ime of PCM.Secondly,through sett ing few BMT customized cache,WLWO swaps the frequent ly accessed data marked entries into customized cache so that the delay o f address translat ion is reduced.In addit ion,the usage o f CRPC(co mpressio n of the replaced po inter chain)in WLWO decreases the frequency to access the replaced po inter during address translation,then the access latency o f PCM is reduced consequent ly.Experiments show that WLWO can increase the life of PCM significant ly wit h less t ime cost by sett ing a small reserved space.To reduce the lo ng simulat ion t ime of LPCMsim,a mult it hreading-based LPCMsim parallel method is proposed in this paper.On the basis o f the group characterist ics of wear-leveling algorithm,the method distributes groups to different CPU cores to make full use o f processing performance o f mult i-core processors fo r the speed acceleration in LPCMsim simulator.LPCMsim preprocesses the trace before simulat ion,that is,the access request belo ngs to different group is distributed to corresponding buffer by dispatcher,while the groups are processed in parallel at the simulat ion t ime and replay their own trace.Experiments show that the simulat io n performance of LPCMsim has been markedly increased by contrast ing original LPCMsim,and the simulat ion speed is proportio nal to the degree o f parallelism.