Study On Hierarchical Storage Structure Design Technology Based On PRAM

To keep pace with the fast growing computing capacity, the memory systems'capacity of high-performance computer system has become larger and larger. The proportion of memory system's energy consumption in computer system's total energy consumption is rising quickly. This is because the present main memory system mainly uses DRAM memory, and the static power consumption of DRAM is very high. With the capacity of DRAM increasing, the energy consumption of the main memory system is increasing. Therefore the research of novel memory structure with large capacity became a hot issue in present computers'memory system field.Phase change random access memory (PRAM) is a novel non-volatile memory, which has many characters, such as good scalability, low leakage current power, high density, bit alterability like DRAM and so on. Because of these properties, PRAM is considered as the best candidate to replace DRAM and to be main memory. But PRAM also has two fatal weaknesses, and the weaknesses are that:1) read operation and write operation are not balanced, the delay and power consumption of write operation are relatively high; 2) the endurance of PRAM is limited.According to the above problems, this paper has carried out the following three aspects:1) This paper summarizes the characteristics and applications of traditional storage technologies and novel storage technologies. Then this paper compares the novel storage technologies, and points out the advantages and disadvantages of PRAM. Finally, this paper studies PRAM in detail, including its principle, analysis and comparison of features and existing problems.2) This paper firstly studies and analyzes a variety of hybrid memory systems based on PRAM. Then according to the properties of PRAM and SRAM, this paper designs a hybrid main memory system with PRAM and SRAM. PRAM with large capacity is the main part to store data. SRAM is the write buffer of PRAM. Moreover, an improved LRFU algorithm is applied to SRAM. As a result, the time delay and the power consumption of the main memory system are reduced. Energy-Delay-Product (EDP) of the hybrid memory is reduced to 40% of the pure DRAM memory. Compared with the pure PRAM structure and the structure using SRAM as Cache, PRAM write operation times are reduced 28.5% and 13%, respectively.3) This paper studies and analyzes existing wear leveling technologies of PRAM, focuses on the analysis of Flip-N-Write wear leveling algorithm. Firstly this paper designs a new algorithm called Shift-Flip-N-Write, which is improved on the basis of Flip-N-Write algorithm. Secondly this paper designs an improved segment swapping technology. So the write operations of PRAM can be balanced, and the life of PRAM can be prolonged. The experimental results show that when the write operation threshold value is 256, the max write counts with Shift-Flip-N-Write algorithm is reduced 61% compared with Flip-N-Write algorithm.