Algorithm And Implementation Of Polar Code Decoding In Low Voltage Power Line Carrier Communication

Power Line Communication(PLC)technology refers to a communication method that uses power line as transmission medium for information transmission.It has the advantages of wide distribution range and no need re-wiring.However,when transmitting high-frequency signal in a complex power line channel environment,the channel will exhibit attenuation,time-varying,Pulse interference,multipath and frequency selective fading,and the transmission of high-frequency signal in the power line will be subject to severe interference and attenuation.Therefore,how to improve the data transmission rate and reliability of power line carrer communication is a very useful and meaningful research project.As the only channel coding method in the world that has been proved to reach Shannon limit,Polar Codes has an important role in increasing the power line carrier communication system capacity and reducing the Bit Error Rate(BER).In order to improve the communication quality and reduce the BER of the PLC system,this thesis puts forward some problems such as noise interference in the PLC system.This thesis completes the design of Forward Error Correction(FEC)codec in the physical layer of low voltage PLC system.On the basis of expounding the key technologies of low voltage PLC system,this thesis studies and explores the theoretical basis of the overall framework of low voltage PLC system,channel polarization phenomenon and codec architecture of polarization code.According to the requirements of baseband system,the polarization code coding algorithm and four decoding algorithms(BP,SC,SCL,CA-SCL)are simulated,the channel coding methods such as LDPC code and Turbo code are compared,the error code performance of algorithm is evaluated,the design parameters are determined,and the performance advantages of polarization code in PLC system are verified.By optimizing CRC check calculation method in decoding algorithm,CA-SCL algorithm is improved,which reduces hardware implementation complexity and improves utilization of hardware resources.By using a semi-parallel structure encoding scheme,the bit flip circuit is omitted,which reducing the number of different or logic gates in the coding module by approximately 56.25%.The thesis uses Verilog language to complete RTL-level design of polarization code codec based on Field Programmable Gate Array(FPGA),to simulate the function of coded circuit and analyze the on-line logic.The simulation and FPGA verification results show that the design of polarization code codec can correctly complete the coding function.Under system clock of 50MHz,the BER of codec circuit is calculated.When Signal-Noise Ratio(SNR)is 3.0dB,the BER is 9.5×10-4 and the result meets the design requirements.Figure[68]table[7]reference[47]...