FPGA Implementation And Optimization Of Convolutional Code And Viterbi Algorithm For Power Line Communication

Power line communication（PLC）is a system based on power transmission network.Transmitting data on power transmission network has its special channel transmission characteristics and noise characteristics.In order to ensure the reliable transmission of digital signal and reduce the bit error rate of digital signal transmission,channel coding technology is generally used.Convolutional coding and Viterbi decoding are effective forward error correction methods,which have the ability to overcome burst errors.Therefore,this thesis focuses on the convolutional code and Viterbi decoding algorithm for power line communication,and focuses on the principle and implementation of convolutional code and Viterbi decoder.Firstly,the principle and representation method of convolutional code are studied,and then the principle and implementation structure of Viterbi decoder are analyzed.On the basis of meeting the standards of power line communication,an improved Viterbi decoder is designed,implemented based on FPGA,simulated and optimized.The main improvements are: aiming at the characteristics of large interference in power line communication,the 3-bit soft decision mode is adopted,which has a gain of2-3d B compared with the hard decision mode;Using the improved branch metric storage and addition comparison unit,the power consumption optimization of 25.5% is obtained at the cost of increasing resource consumption,but it is still enough to meet the requirements of g3-plc standard of power line communication.