Research On Secure Communication Method Of Internet Of Vehicles Based On Error Correction And Encryption Code

As the number of motor vehicles in cities continues to grow,urban road traffic safety issues are becoming more and more prominent.Since the Internet of Vehicles can realize the interconnection between vehicles and vehicles,vehicles and roadside infrastructure,it has shown great potential in solving road safety problems.In the application of the Internet of Vehicles,the data encryption part is not clearly specified,and the channel coding scheme in the existing V2 X communication standard is not suitable for certain specific vehicle network application scenarios that need to send a large amount of short control information code.In response to the above problems,this thesis proposes an encrypted communication scheme suitable for short-code communication in the Internet of Vehicles environment,and implements it based on FPGA to reduce the end-to-end latency.First of all,this thesis introduces the development of the Internet of Vehicles and the problems it faces,and proposes a security communication scheme for the Internet of Vehicles suitable for short code scenarios.The encryption part of the scheme adopts a hybrid encryption scheme combining ECC and AES.The AES part can also resist first-order DPA attacks;the channel coding part adopts(31,16,7)QR code,which is more effective than LDPC for short code communication.Based on the communication scheme,this thesis gives the FPGA implementation architecture,optimizes the hardware of related algorithms,and completes the detailed logic design of each module.For the elliptic curve encryption module,the finite field multiplication is optimized for the hardware,so that it can complete the modulo operation at the same time during the multiplication operation;the modulo squaring algorithm is also optimized,so that the modulo squaring operation can be completed within one clock cycle;The Fermat theorem is optimized to reduce the original 161 times modulo multiplications to 9 times,which greatly speeds up the calculation speed of solving modular inverses.Finally,the time to complete a dot multiplication operation is 1.85 ms.For the AES encryption module,firstly,the S-box was redesigned to make it resistant to DPA attacks without changing the AES output;secondly,two pipelines were designed for the round function and key expansion function to achieve high-speed encryption During the process,the final operating frequency is 426.31 MHz,and the throughput rate is 54.57 Gbps.For the QR encoding module,according to the characteristics of the OCW algorithm,three parallel pipelines are designed,the decoding delay is only 4 clock cycles,and the highest frequency is 443.31 Mbps.Finally,the ECDH key exchange module,AES encryption module and QR codec module designed in this thesis are simulated in Modelsim and board-level tested on Cyclone V5CGXFC9D6F27C7.The results show that the logic function of each module is correct,and the AES encryption module can resist first-order DPA attacks.