The Research On Single Event Transient Hardware Emulation Technology

With the development of integrated circuit technology and the increase of working frequency,the problem of Single Event Transient(SET)in digital circuits is becoming more and more serious.At present,the research of SET is mainly done by the way of fault injection simulation.With the reduction of the feature size of semiconductor devices and the increase of circuit scale,a new situation has emerged in the simulation of SET effects,as follows:(1)The interconnect delay accounts for a greater proportion of the circuit's total delay.However,the existing method of simulating SET only pays attention to the delay of the logic gate and neglects the influence of the delay of the interconnect line,resulting in inaccurate prediction the width of the SET pulse.(2)When a SET pulse arrives at multiple storage units via different paths,it will result in multiple-bit-upset(MBU),thus making the soft error rate evaluation result high;In addition,when there are multiple loads on the node,the logic gate delay will change accordingly,making the multipath MBU study caused by SET more complicated.In order to effectively evaluate the effects of the SET effect on the circuit reliability,this thesis considers the effects of line load,logic gate delay,and multipath propagation in the circuit based on the traditional hardware fault injection system.And this thesis will optimize the model from the three aspects(included SET pulse generation,SET transmission,SET latching).For modern ultra-large-scale circuits,FPGA-based hardware emulation is proposed to achieve analog acceleration.The main work of this thesis is as follows:1.The trend of the pulse width of SET with the length of the interconnect is studied.Through SPICE simulation,a function model of the change of the SET pulse width of the basic logic gate with the length of the interconnection line is proposed to realize the prediction of single-event transient pulse width of the gate unit.In the 130 nm and 90 nm processes,the model is applied to a variety of basic units to verify the effectiveness of the model.SPICE simulation results show that the maximum error of theoretical calculation and simulation results is 6.09% and the minimum is 0.37%,which improves the accuracy of single-event transient pulse width prediction and lays a foundation for the following transient pulse width prediction.2.For the multipath MBU phenomenon caused by SET in the circuit,a simulation verification platform is built for analysis.In the aspect of transient pulse generation,considering the influence of node fanout on SET injection pulse,an improved pulse injection model is proposed.In terms of propagation delay,considering the influence of line load on the logic gate delay,the modeling of the quantized delay model is completed,and the simulation of the electrical transmission characteristics in the circuit is realized.In terms of latching,the contribution of the multipath MBU to the latch probability is analyzed and a modeling analysis is performed.Finally,a multipath MBU phenomenon in the circuit is analyzed by building a hardware emulation and verification platform.3.On the ISCAS-85 reference circuit,this thesis verifies the effects of interconnect delay and multipath MBU in the circuit.Experimental results show that most circuits have multi-path MBU phenomenon,and different circuits have different degrees of severity.This is due to different loads in the circuit.By studying the multipath MBU phenomenon,we can observe the damage degree of the system after single-event transient pulse occurs in the circuit and evaluate the reliability of the circuit.At the same time,the influence of the interconnect delay in the circuit on the single-event transient pulse effect is verified.Finally,the variation of the output error rate caused by the SET in the circuit with its operating frequency is simulated.