The Research And Design Of A 20-bit SAR Adc Using Oversampling Approach

With the rapid development of sensors and digital processing technology,Analog-to-Digital converter(ADC)has fast become an important module of electronic equipment and sensor readout circuits.Low power and high precision ADC has become the main development trend of Analog-to-Digital Converter(ADC).Successive Approximation Register(SAR)ADC is used vastly in sensor application because of its advantages of low power and simple architecture.Due to the limitation of the integrated capacitor matching accuracy,the single-stage SAR ADC is difficult to meet the requirement of high resolution,so it is necessary to integrate multistage to improve the resolution of the whole system.In addition,the total capacitance value increases exponentially with the number of bits.Besides,there occurred a wide spread of capacitance values that will lead to severe capacitance mismatch.Consequently,for SAR ADC to complete a conversion,it has to go through a designated number of clock cycles sequentially before it can output a valid data.This primarily set the speed limit of the SAR ADC.To solve the above problems,this thesis proposes a two-stage SAR ADC that uses oversampling technique to increase the resolution,C-2C capacitor structure to achieve good capacitance matching,and pipeline operation to shorten the conversion time of the ADC system to achieve high resolution,high accuracy,fast conversion time and cost-effectiveness objectives.With power supply voltage of 5V,sampling frequency of38 kHz and input signal frequency of 1kHz,simulation results show that a total power consumption of less than 15 mW,an integral nonlinear(INL)of less than 0.5 LSB,and an ENOB of more than 19 bits are achieved.