Design Of Reconfigurable Cipher Coprocessor

The realization of the internal cipher algorithm in processor can guarantee the security of the chip data chain communication link information.Compared with the software implementation based on operating system,the hardware implementation of cryptographic algorithm takes the advantage of faster processing speed,higher safety performance characteristics.Different security applications derive a variety of cryptographic algorithms,which express different computing tasks,characteristics of different algorithms operate expression computing tasks is not the same,and therefore these conditions produce diverse demands for hardware implementation.Because of the stable structure of the system,it is not realistic to represent all the features.Furthermore,instruction level algorithm has characteristics of complex logic design and low throughput.Dedicated ASIC chip for the algorithm has high throughput with full custom design,but it has the disadvantages of singularity,poor flexibility and high design cost.In view of the above problems encountered in the hardware implementation of the algorithm,this thesis designs a reconfigurable cryptographic co-processor.In this thesis,the research and engineering practice are as follows.1)In this thesis,the reconfiguration optimization of self structure is carried out in the typical block cipher DES,AES algorithm,SM4 algorithm,a typical SHA Hash function.After mapping the structure of the resource consumption can reduce by 50%.2)Aiming at the most frequently used operation in cipher algorithm,the thesis designs a reconfigurable cipher basic unit model RU,and it made on this basis performance optimization.And on this basis made according to different performance optimization: mapping the block cipher structure is given priority to with high performance,mapping the Hash function,the interconnection structure is given priority to with low area.3)A TRNG(true random number generator)with higher security is designed,which generates a series of random detection passed the NIST standard random tests.The SHA3-512 Hash function ensure the security level reach 2256.This is the highest level of security.4)Design synchronous FIFO and asynchronous FIFO,and make timing optimization for the port of the synchronous FIFO.5)Design the cipher co-processor structure,and it can efficiently and flexibly complete the purpose algorithm operation,through receiving bus configuration.