Properties Rearch And Optimization Of 60V Power UMOSFET

Power semiconductor devices are the core devices for power conversion in power electronic systems.MOSFET has important application status in the consumer electronics and industrial electronics industries,especially the development of electric vehicles,automotive electronics,and smart cities,leading to a significant increase in demand for power MOSFETs.UMOSFET(Ultimate Trench U-shape Metal-Oxide-Semiconductor Field-Effect-Transistors)has been widely used due to its small chip area,low on-resistance,and high switching speed.One of the major technical challenges facing UMOSFET devices is to reduce the device's on-resistance while ensuring a sufficiently high breakdown voltage.This has also become the main development direction of current power UMOSFET technology.This article has carried out related research on this technical challenge.The specific research content is as follows:(1)The structure and process parameters of the power UMOSFET significantly affect its key performance indicators such as on-resistance,threshold voltage,and breakdown voltage.With the theoretical analysis and simulation of UMOSFET on-resistance,threshold voltage,breakdown voltage and other key parameters were optimized design in this paper.(2)The thickness and doping concentration of cell structure epitaxial layer,device trench depth,thickness of gate oxide layer,and the influence of Pbody region implantation on device performance are studied and optimized design.The 60 V UMOSFET device and its JTE edge are designed.By using the JTE edge instead of the traditional field plate field plate edge,a larger cell area is obtained in the chip,so that the overall on-resistance of the chip is reduced.The performance is further improved before the comparison and optimization,and the overall layout of the chip is completed,and the types and methods of several chip layouts are given.(3)A new structure cell of a 60 V UMOSFET chip is designed,a UMOSFET cell with a P-pillar region is designed,and the newly added P-pillar region is simulated and optimized,which improves the performance of the conventional UMOSFET device and improves Traditional UMOSFET device voltage resistance ratio relationship.