Research On Mapping Algorithm To Optimize Lifetime Of Network-on-Chip

With the ever-increasing demand for computing speed of electronic devices,single-core processors have moved toward the era of multi-core and many-core processors.Due to the limited bandwidth and scalability of traditional bus-based interconnection methods,the improvement of performance is affected.On-chip network(NoC)can provide higher bandwidth and strong scalability to take the place of traditional bus,NoC has become the mainstream option of interconnection method of on-chip multi-core system.However,as integrated circuits evolved to deep sub-micron and below,the shrinking of process lead to a great threat on life reliability,which is due to the aging mechanism such as electromigration(EM).Therefore,lifetime reliability is accompanied by the development of on-chip networks.As one of the research hotspots.This thesis models the lifetime reliability of the on-chip network path based on the EM aging mechanism,and then uses the application mapping algorithm in the system-level design technology to balance the aging condition in the on-chip network,thereby optimizing the lifetime of the on-chip network.Firstly,this thesis evaluates the impact of the existing mapping algorithm on the network aging imbalance,and proposes a lifetime reliability assessment model based on the electromigration failure of the on-chip network path.The simulation runs different mapping algorithms with the network aging conditions are different.It can be analyzed that the mapping algorithm has a great influence on the longevity reliability and the factors affecting the aging imbalance are related to the path usage rate.Lifetime reliability assessment model is based on the on-chip network path electromigration failure and lifetime budget of each path in the on-chip network is analyzed.Then,based on the lifetime reliability assessment model,an application dynamic mapping algorithm to optimize the lifetime of the on-chip network is proposed.The dynamic mapping algorithm is used to balance the aging of the entire on-chip network by selecting a mapping node to measure the reliability metric of lifetime,thereby prolonging the service life of the on-chip network.The algorithm is mainly divided into a head node selection algorithm and a life-time mapping algorithm.The head node selection algorithm can be combined with a variety of existing mapping algorithms,and its feature is to enhance the reliability of lifetime on the basis of preserving theoptimization characteristics of the existing mapping algorithm itself.The mapping algorithm is an application mapping algorithm that is specifically designed to optimize lifetime reliability.It optimizes the on-chip network lifetime without introducing additional processor and on-chip network dynamic power consumption and delays.Finally,this thesis designs and builds an on-chip multi-core system verification platform,and it simulates the portable first node selection mapping algorithm and life optimization mapping algorithm proposed in this thesis.The simulation results show that compared with other classical mapping algorithms under different system utilizations,the life-optimized mapping algorithm proposed in this thesis greatly improves the minimum MTTF of the system and the mean and variance of the overall system MTTF,it prolongs the system lifetime.And there are no significant differences or even decreases with other mapping algorithms in the two indicators of network packet delay and average Manhattan distance.The simulation results indicate that the performance of proposed algorithm is good.