| As the feature size shrinks,electromigration(EM)becomes a more critical reliability issue in IC design.The problem becomes more severe for power delivery networks as they experience large unidirectional currents and thus are more susceptible to EM effects than signal wires characterized by bidirectional currents.However,existing EM modeling and analysis techniques are mainly developed for a single wire.For practical chips,the power grid networks typically consist of multi-brance metal segements.As a result,more accurate EM modeling and analysis techniques are required to ensure sufficient accuracy without sacrificing the efficiencies.In this work,this paper have derived the analytical expressions describing the hydrostatic stress evolution in several typical interconnect trees.And EM was studied on different multiple via structures.Finally,this paper introduce a design EM-aware interconnect reliability technology that provides a scalable,full-chip EM analysis that consider interconnect resistance,the current density,and nodal hydrostatic stress analysis for failure prediction.The simulation results proves that redundant via is one of promising solutions on migrating EM degradation.With more via along metal line direction,the current density and temperature gradient under via can be reduced and improve the EM lifetime.From 1x1 to 1x3 structure,the MTTF increased by 52.14%;From 1x3 to 3x3 structure,the MTTF increased by 14.04%.Our results suggest that 1x3 structure is the best tradeoff between routing area and EM life-time.And this paper have derived the full-chip analysis model in practical layout,the results proves that the peak value of hydrostatic stress is reduced by 49.29%,the average value of stress is reduced by 44.28%,and the standard deviation is reduced by 43.04%.This shows that the 1x3 via structure can effectively improve the EM lifetime.This work provides theoretical support for using the redundant vias to improve reliability in design. |
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