Research And Design Of Addressable Test Chip For MOSFETs In Standard Cell

With the evolution of semiconductor technology,the feature size of integrated circuits has been scaling down.In advanced nanotechnology,the complexity of the manufacturing process leads to MOS transistor instability or even variations.The drastic variation of transistor characteristics poses a challenge to the reliability of the device model.It is more and more important to study addressable test chips with high accuracy and area utilization for transistor parameter extraction and performance detection.Standard cells are the basis of digital circuit.Each transistor in a circuit has a specific environment.Providing transistor in standard cell a relative environment in test structure would not only establish an accurate process parameter model and variation model,but also make prediction on standard cell performance.It plays a crucial role on improving process yield and product yield.In this thesis,we focus on standard cell and its MOS transistor characteristics,and do research on large addressable MOSFET test chips with high accuracy and area utilization as follows:1)Addressable test structure is proposed according to the requirement of MOSFET parameter extraction,deviation detection,and advanced technology modeling.2048 transistors can be placed in this test structure with only 15 I/O PADs.Each performance parameter can be measured including Ioff,Vth,Idsat,Idlin.Also,it is a metal 2 testable structure,which significantly reduces testing cycle.This addressable MOSFET test chip has been silicon proved to be a fast and accurate test structure by 16nm FinFET process.2)Due to MOSFET surrounding environmental requirement,test structure is designed to keep MOSFET FEOL and MEOL unchanged from original standard cell layout,BEOL metals will be slightly changed according to routing requirement.This method will restore the standard cell environment as much as possible to make testing results more accurate,which would reflect the authentic performance.3)Manual work on test structure layout proposed in 2)costs huge labor and time,also easily results in design rule violation.In this thesis,an automated flow to identify,extract the test structure from existing standard cell layout is proposed,also this flow provides routing solution from test structure terminals to addressable circuit terminals.This flow can be applied on FinFET technology as well.