Research On Key Techniques For CMOS AFE Receiver In Power-line Communication

Power-line communication is a technique that uses the existed power line to communicate or transfer data.Such that it offers the cheap media to communicate Because of its no need of specialized telecommunication line,PLC reduces the cost of the communication drastically.When compared to other communication methods,it is cheap,feasible and also convenient.But the channel or the power line is easily affected by the noise.It also has a poor impedance matching character.These all above lead to the harsh communication environment.To satisfy the standard of the communication,we should design a highly reliable structure to guarantee the accuracy of the data and information.As the critical component,the receiver and also the analog to digital converter?ADC?need to be designed and optimized reasonably.This thesis proposes a high dynamic range,wide bandwidth receiver for power line communication.It is composed of a 4 stage R-2R attenuation network,a gain programmable low noise amplifier,a 4^th order low pass filter with cutoff frequency of lager than 100MHz and a programmable gain amplifier.Among these components,the attenuation network provides an attenuation of 6.02dB per tap and the resulting control function is linear in dB.The amplitude response is flat within�0.5 dB from dc to100MHz.The LNA use the FBDDA?fully balanced differential difference Amplifier?as the core amplifier to reduce the thermal noise contributed by the feedback resistors when compared to the traditional amplifier.The Class-AB output stage also helps to improve the current driving efficiency.The low pass filter is designed so we can trim the bandwidth by the digital controlled capacitor banks.It also has the-80dB/decade roll-off.The programmable gain amplifier is accomplished by the digital words controlled feedback resistors network.It achieves a gain range of 0d B-15dB with 3dB step.The circuit was realized in the SMIC 0.18mm CMOS process and the power supply is 3.3V.We fulfill the layout and the post simulation results show that the receiver can achieve the3dB bandwidth of larger than 100MHz.The dB-linear range is-18dB to 33dB with the maximum gain error of 0.5dB.A third harmonic distortion?HD3?of better than-83dB@5dBm input signal in 7MHz.The LNA provides an input-referred noise of1.6nV/Hz^1/2.Connecting the analog signal to the digital world,ADC plays the role of bridge.It transfers the analog signal to digital words so as to the computer could process.Its accuracy and speed decide the quality and speed of the communication.Here we firstly analyse the non-binary weighting method and the binary-scaled compensation weighting method,then combined with the split DAC array,we apply the binary scaled capacitor recombination method,the IMCS switching method and the asynchronous control logic,based on the low noise dynamic comparator and digitally accomplished calibration method,we design a 12 bit,125MS/s SAR ADC.It outperforms in the power and the area than the already known structures.Designed in TSMC 65nm 1.2V CMOS process,we fulfill the post simulation of the whole circuit.Under the sampling rate of 125MHz,the post simulation results show the DNL is between-0.38LSB and 0.23 LSB,the INL is between-0.43LSB and 0.42LSB.When the input is 10.09MHz sine wave,the FFT result shows the SNDR is 72.3dB,SFDR is 84.1 dB,the resulted effective number is 11.72 bits.It occupies an area of 400mm?390mm,the total power consumption is 5mW,the FOM is12fJ/conv.