The Design Of A Low FOM 10-bit High-Speed SAR A/D Converter

In a few decades ago,Successive approximation register?SAR?analog-to-digital converters?ADCs?have been proposed,but interested in such topologies in recent years.The reason is that compared to other ADC architectures,SAR ADCs have the advantages of smaller area,simpler structure,lesser analog modules and lower power consumption.On the other hand,with the CMOS feature sizes scaling down,the supply voltage of circuits and the device's intrinsic gain are also gradually decreased,which is difficult to achieve high-gain and high-bandwidth op-amps,and that is a great challenge for Pipelined ADCs which require high-gain and high-bandwidth op-amps.SAR ADCs don't need op-amps,and its process adaptability is great.Nowadays,high-speed low-power SAR ADCs are in high demand for portable electronic systems and laser ranging.This paper presents an energy-efficient successive-approximation analog-to-digital converter?SAR ADC?design that targets for 1.8-V,10-bit 100MS/s performance.Bootstrapped switches make transistor's on-resistance be constant that could improve the sampling linearity.In order to weaken the charge injection,a PMOS is connected to switching transistor which would combine with the electrons in channel.To reduce energy consumption,a new switching scheme combined with spilt-capacitor switching scheme is proposed which taking advantage of decreasing the capacitors in DAC array by using the LSB capacitors.For a 10-bit SAR ADC,the proposed switching scheme only requires 2⁸C₀and consumes 47.7CV²_REF.And compared with the conventional switching scheme,the proposed scheme can reduce the energy consumption by 96.5%.In addition,it didn't use V_CM neither in the determination of the first two bits?the MSB and 2nd-MSB bits?nor the conversion process.The proposed two-stage dynamic comparator consists of a dynamic pre-amplifier and a dynamic regenerative latch,which could reduce the offset voltage,kickback noise and power consumption.In SAR ADCs,the SAR logic controller delay is a limitation on the increase of the ADC conversion rate.In order to improve conversion rate,this paper design a new SAR control logic that could be suitable to high speed SAR ADC.In order to avoid using external high frequency clock which may increase the difficulty of design and degrade converter's performance,the asynchronous logic is used.The 10-bit 100-MS/s SAR ADC is fabricated in SMIC 180-nm 1.8V CMOS process with metal-isolator-metal?MIM?capacitor option,the total ADC core occupies an active area of476*445?m.The SAR ADC achieves an ENOB of 9.83-bit and consumes 9.62mW,resulting in a figure of merit of 105.6fJ/conversion-step.