The Research Of Reconfigurable Array For Visual Information Processing And Parallel Image Enhancement

Visual information processing algorithms are usually data-intensive or computation-intensive.With the development of multimedia technologies,these algorithms are becoming more complex.The hardware architecture' real time capability is needed for visual information processing applications.And the period of the innovation and optimization of algorithms is shorter,so the flexibility is also critical for these hardware architectures.Now the general-purpose processors and ASIC can't satisfy the former requirements.The reconfigurable processor is an alternative to solve the problem since there is a configurable multi-PEs which is suitable for parallel computation of algorithms.It is also flexible since the configuration can be changed easily.This paper discusses the basic reconfigurable computing architecture and some state of art reconfigurable architectures.And we develop a multi-grained reconfigurable PE array which is mainly intended for coarse-grained computation and has some fine-grained operators.It has 13 basic operators to complete the visual information algorithms.A 4*4 processing elements array is developed to decrease the complexity of algorithms mapping,and machine cycle is defined to solve the synchronous issue of different PEs.Local interconnection is applied in the router module to make prudent use of hardware resources.The data memory is divided into 4 banks,and each of them is connected with an arbiter.In this way,the visual information in different banks can be accessed simultaneously.Broadcast mechanism is also applied in the memory arbiter.A set of configuration messages are developed and “iteration” field is used in three levels: the processing elements array,the processing element configuration pack and the processing element configuration word in order to condense the length of configuration messages.And some low power techniques such as clock gating,multi-voltages are applied for optimization of processing elements.Based on the developed architecture,we make study on the image enhancement parallel pipeline techniques.Median filter and gray world algorithm are mapped onto the reconfigurable array according to the following principles: parallel computation and high effectiveness of data interconnection and accessing.And the speedup is 6.90 and 7.68 compared with Atom 230 which verify the reconfigurable architecture' performance.An improved noise removal filter for color images is proposed,and experiments show that this method can effectively remove impulse noises and protect the details in color images with the noise density varying from 10% to 80%.