The Research And Design Of The Reconfigurable Processing Element Array For Visual Information Processing

Reconfigurable processor is a new type of processor based on general purpose processor and ASIC,reconfigurable processor has the advantages of changing the way of processing,at the same time has a high performance,thus it gets extensive attention in many ways.For video image processing,the performance of coarse-grained reconfigurable processor is excellent,thus it becomes a substitute for the general processor and ASIC.Reconfigurable processor is still in its infancy,research is less at home and abroad.Based on the structure of several mainstream reconfigurable processors,the reconfigurable processor for visual information processing is studied and designed.This thesis first studies and analyzes the current classical reconfigurable processors from the function of Processing Element(PE),configuration word,interconnection topology.Combined with the characteristics of the visual information processing algorithms this paper carries out the design of the Processing Element Array(PEA)targeted for visual information processing.There are 13 kinds of basic operation in PE,which can satisfy the basic requirements for visual information processing.PEs are synchronized by external controller to ensure the accuracy of the data interaction.There are three levels configuration for the array,the configuration of PEA,the configuration of PE and the configuration of PE in every machine cycle.Every configuration includes control information from PEA,the specific operation of each machine cycle.et al.On iteration,three configuration levels all have an iteration field to compress configuration,which can be used to reduce configuration time.Storage unit adopts the structure of multi-RAM to reduce access conflict from PEs,and the unit has broadcast mechanism.This paper puts forward three kinds of interconnection topologies for PEA,and sets up an interconnection network topology exploration of coarse-grained reconfigurable array on FPGA.It is used to verify the performance of different algorithms in different interconnection topologies,which can help us to select interconnection topology of PEA.According to the design of PEA above,we write hardware code and simulate it by Modelsim and ISE to prove that the structure can accomplish the designed function.