Monitoring Automation In SoC Design And Verification

Due to the rapid development of IC manufacturing process,the scale of System-on-a-Chip(So C)is growing huger and huger,and it has resulted in the increasing difficulty of integration and debugging.Thus at the beginning of a So C development,designers would like to provide some “key signals” which can show the internal characteristics of each module for the use of future debug.Due to the limited resources of the So C pin,according to the principle of time division multiplexing,only a limited number of debugging signals can be sent out at a time.And the function of the So C signal monitoring module is that based on a debugger's configuration of the registers,the specified key signals within a specified module can be routed to the output pin of the chip,then debugger can do the observation and analysis of the underlying signals though an external display device(such as logic analyzers,etc.).And the signal monitoring module is actually the cascade of multiplexers.In the past,the signal monitoring module is designed,integrated,and verified manually according to the project.And then you need to generate monitoring-signal's tables which contain all the monitoring signals' hierarchs and names using the EDA tool(like Verdi or VCS),and you also need to push each module's designer to check and fill the “signal function” column of the table.Finally you can share the table to post-silicon verification team.There are a lot of repetitive works in this workflow that can be replaced by writing some scripts.In order to optimize the above workflow,based on EDA,software engineering and the practice of baseband So C R&D project,this paper explored the automation flow of the signal monitoring module's design and verification.After fully understood the knowledge of the module,I wrote some scripts using the programming language(Python and Tcl/Tk)to interactive with EDA tool,and at last it realized a more simple,efficient,robust and reusable workflow.Using the automation method raised by this paper,a series of tasks can be done by printing just one command including generating the module's design and verification files,invoking simulation and analyzing result logs;and the monitoring-signal forms can be done quickly and easily by interacting with the GUI.It has been proven by the practice that the automated method developed in this paper can significantly improve the efficiency of design and verification personnel,saving manpower and time costs.