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Comprehensive Automation Of SoC Design And Verification Based On VHDL

Posted on:2017-07-10Degree:MasterType:Thesis
Country:ChinaCandidate:X G WangFull Text:PDF
GTID:2348330488474613Subject:Engineering
Abstract/Summary:PDF Full Text Request
Followed with the Moore's law, semiconductor industry keep on changing. IP reuse technology makes the rapid increase of the integrated function on chip, fabric represented by So C are becoming complexity day by day, which bring huge effort to IC front-end design and verification. For ensurence of time-to-market, the development period of project are getting shorter, so it is common to see multi-project proceed in parallel or in pipeline. Design as well as verification engineer are facing severe stress. In order to improve the efficiency and quality of design and verification, automation is feasible means must be taken. Therefore, this paper proposes the use of automated scripts and tools as a solution.Content in this paper are based on real project of a company where I worked in as an intern, take System Control Unit in So C as an example, makes a brief introduction of the overall function of SCU, and highlight the main function: Reset Management.For design, due to the reset management has strong regularity, the condition of automation is satisfied. So we can use script to generate RTL code of common reset model. we also introduce how to use tools to auto-generate sub-module interconnecting hierarchy and reg block.For verification, the function simulation of any block and IP rely on testbench, to save time on building testbench, we use script to make it automated. Testcase is the implementation of Verification-Object, which include input stimulus and output checker. Reset module accepts multiple reset sources and output more than a hundred reset signal, it is very complicated to write lots of testcases to cover all scenario, so we also use script to generate them.Finally, in order to verify the correctness of the automated code, we use both TB-based function simulation and none TB-based formal verification, to ensure all the code meet the requirement.Currently, the automation is more stable through the design and verification in different projects. To reuse scripts in different projects, user only need to do small necessary adaption of them.
Keywords/Search Tags:SoC, Time-to-Market, Automation, System Control Unit
PDF Full Text Request
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